In a typical memory system of a computer system, a memory controller facilitates the access of a memory module in the computer system. The memory module may include one or more memories that are referred to as ranks. The memory controller communicates with the ranks of the memory module via input-output (I/O) interfaces and transmission lines. The I/O interfaces exist at both the memory controller end and at the memory module end. The memory controller transmits via its I/O interfaces a host of signals to the ranks including address signals, control signals, clock signals, etc., to access data from the ranks or to send data to the ranks.
For correct communication between the ranks and the memory controller, termination impedance is set on the I/O interfaces of the memory controller and/or the ranks. The term correct communication herein refers to sending and/or receiving expected data between the memory module and the memory controller, where the expected data meets performance specifications e.g., timing, voltage margin, signal integrity, etc. The value of the termination impedance determines the quality of the signal being communicated between the memory controller and the ranks.
Typically, during memory access (e.g., memory read) initiated by the memory controller, a termination impedance of the I/O interface at the ranks is set to a value for reducing noise on the signal being communicated between the rank and the memory controller. For a Double Data Rate 3 (DDR3) I/O interface, the memory controller is only operable to set the termination impedance on the DDR3 I/O interface of the ranks being accessed to a single finite termination value. The termination impedance for DDR3 I/O interface of ranks not being accessed is set to a high impedance value (infinite impedance caused by tri-stating the termination devices) as a default termination impedance value.
One reason for having the default termination impedance value for the DDR3 I/O interface as a high impedance value is to save power consumption. DDR3 I/O interfaces are required by specification to have a center-tap termination scheme having a pull-up termination resistor connected to a power supply node and a pull-down termination resistor connected to a ground supply node. Such a center-tap termination scheme provides an electrical path from the power supply node to the ground node via the pull-down termination resistor and the pull-down termination resistor. The electrical path is a source of power consumption when the center-tap termination scheme is enabled.
To reduce power consumption on the DDR3 I/O interface when there is no memory access on a rank, the termination impedance of the rank remains at default value of high impedance. Such high termination impedance (i.e., infinite impedance) reduces timing and voltage margins on the read signals being communicated between the memory controller and other active ranks. As demand for higher speeds of memory I/O interfaces is increasing e.g., DDR3 I/O interface speed of 1600-3200 Mega Transfers per second (MT/s) vs. 800-1600 MT/s for Double Data Rate 4 (DDR4) I/O interface, a default value of high termination impedance reduces memory system performance.